School Address
Permanent AddressMcFarland, Apt. 4E
16868 SE Oatfield Rd Escondido Village
Portland, OR 97267 Stanford, CA 94305
(503) 659-9869 (650) 497-3887
hegar@cs.stanford.edu
School Address Permanent Address
McFarland, Apt. 4E 16868 SE Oatfield Rd
Escondido Village Portland, OR 97267
Stanford, CA 94305 (503) 659-9869
(650) 497-3887 hegar@cs.stanford.edu
Computer engineering summer internship, July 1998 - September 1998.
MS in Computer Science, expected December 1998
Systems Specialization -- Networks, Video, and Logic Design emphasis
Stanford University -- Stanford, CA
BS in Computer Engineering, March 1997
University of Washington Honors Program -- Seattle, Washington
GPA 3.80/4.0 -- With College Honors
Course work completed as of June 1997:
Programming -- C / C++, LISP, ML, and Prolog, Discrete Structures, Data Structures
Hardware -- Digital System Design including implementation with PALs, PLAs,
FPGAs, Microcontrollers and other discrete components.
Electrical -- LRC Circuits, MOSFETs, CMOS logic, BJT amps, Op-Amps
Mathematics -- Calculus I, II, and III, Differential Equations, Linear Analysis
Other experience -- Technical Writing, experience with Windows, DOS, Windows NT,
Windows '95, Unix, the World Wide Web, HTML, and Visual Basic.
TEKTRONIX SOFTWARE DEVELOPMENT FOR MPEG2 CODEC, 3 / 97 - 9 / 97
Tektronix Inc, Advanced Development -- Beaverton, Oregon
Wrote the software driver for a prototype MPEG2 decoder board.
Designed a feedback algorithm to correct clock drift between an MPEG2 encoder / decoder
pair connected via ATM.
Extracted uncompressed audio from the on-board audio mezzanine and gathered CPU
utilization data to determine the system requirements as the audio is scaled up.
Wrote software which retrieves the raw data sent out on the video vertical blanking interval
and parses that data to extract formatted closed captioning.
Setup demos and wrote software which allowed Tektronix to demonstrate low latency video
over ATM at trade shows like SuperComm.
INTEL FIBRE CHANNEL DEVELOPMENT, Summer 1996
Intel Corporation -- Hillsboro, Oregon
Investigated Fibre Channel as a cost effective, Gigabit per second I/O solution for
Intel's scalable, parallel servers.
Integrated Fibre Channel hardware from a variety of OEMs into a test station from which
loop integrity, bandwidth, and throughput of data transfers can be examined.
Helped to implement tests that enable Intel to compare Fibre Channel to other common I/O
platforms, such as SCSI, Ultra SCSI, and PCI.
Gave considerable feedback to vendors of prototype Fibre Channel hardware to help ensure
that the industry continues its rapid Fibre Channel development and that Intel will be
in a position to take advantage of that technology.
INTEL SSD SUMMER INTERN, Summer 1995
Intel Corporation -- Hillsboro, Oregon
Internship in the Scalable Systems Division of Intel building, testing, and integrating
the Intel Scalable Parallel Multimedia Server.
Helped to scale the parallel multiple processor / multiple disk system on which the
Media Server operates.
Worked with and tested prototype compute nodes driven by state-of-the-art P6 processors
utilizing ATM OC-3 technology.
Custom installation of off site systems for Intel customers
Organized and kept inventory control of the hardware in the IMS laboratory
CAM PROGRAMMER / WATER-JET OPERATOR, Summer 1994
Hegar Manufacturing, Inc. -- Portland, Oregon
Programming of ultra-high pressure water-jet cutting system using Computer Aided
Manufacturing
Operation and upkeep of water-jet machinery
Successfully assumed complete responsibility for shipping/receiving and sales for a
period of one and a half months
Polhemus Scholarship through the Stanford Department of Engineering 1997-98
Honors Program at the University of Washington, graduated "With Honors"
NASST Scholarship for outstanding potential as an engineer.
Member of Tau Beta Pi National Engineering Honor Society