Summary for H&P Ch. 6

Sector Smallest unit of access on a disk. A track is broken up into sectors.

Track Concentric circles that divide up a disk platter.

Platter Magnetic disc that holds information. A hard disk may be composed of multiple platters.

Cylinder Tracks directly above and below each other on all platters.

Average rotation time 0.5/RPM

Transfer time The time it takes to transfer a block or blocks of bits. Depends on block size, rotation speed, and recording density.

Read ahead Sequential precaching at the disk level.

Controller time The overhead imposed by a disk controller.

Bus Adv: low cost and versatility. Dis: communication bottleneck.

I/O bus Generally long and slow to support a larger number of I/O devices.

Memory bus Short and fast.

Bus transaction Two phase transaction on the bus that consists of expressing an address and then sending or receiving data.

Bus Design Decisions

Option	High performance	Low cost
Bus width	Separate address and data lines	Multiplex address and data lines
Data width	Wider is faster	Narrower is cheaper
Transfer size	Multiple words have less bus overhead	Single-word transfer is simpler
Bus masters	Multiple (requires arbitration)	Single master (no arbitration)
Split transaction?	Yes - separate request and reply packets get higher bandwidth (need multiple masters	No - continuous connection is cheaper and lower latency
Clocking	Synchronous	Asynchronous

Synchronous bus The bus includes a clock in the control lines and all events happen relative to the clock.

Asynchronous bus The bus is self-timed and uses handshaking protocols instead of a clock.

Memory-mapped I/O Reads and writes to a particular location in memory are actually used to access I/O devices.

I/O opcodes Special CPU instructions are used to read and write I/O devices. Used instead of memory-mapping.

Interrupt driven I/O I/O device interrupts CPU when long I/O is done.

DMA Direct Memory Access. Transfers data between memory and and I/O device while the CPU does other things.

Reliability, Availability, and RAID

Reliability The probability of some part of a system being broken. Can only be improved by improving environmental conditions, using more reliable components, or using fewer components.

Availability The probability of the system being available for use by clients.

Striping Writing data over an array of disks.

RAID level 1 Mirroring. All writes are written to a backup disk.

RAID level 3 Bit-interleaved parity. One disk is an exclusive parity disk. The cost for this scheme is 1/N where N is the number of regular disks.

RAID level 5 Block-interleaved distributed parity. Small writes don't pay as much of a penalty as with RAID 3. On a write, the blocks affected by the write are read from the disk, then written and only the corresponding parity bits are changed. The parity information is distributed over all disks so that no one disk becomes a bottleneck.

Interfacing to the OS

Stale data The CPU or I/O system could modify one copy of memory without updating others. If the I/O system is connected to the cache, DMA's may flood the cache with values that will be unused by the CPU. If the I/O is not connected to the cache, stale data will be a problem.

Two parts to the stale data problem:

The I/O system sees stale data on output because memory is not up to date. This can be solved by making the CPU cache write-through. Alternatively, a write-back cache will work if the OS flushes cache entries to memory before doing a write to an I/O device.
The CPU sees stale data in the cache on input after the I/O system has updated memory. To solve this, the OS can evict conflicting cache lines on an I/O input. Another solution uses hardware to automatically invalidate cache lines that conflict with an I/O input.

DMA and virtual memory Complications can arise as to whether DMA should transfer using virtual or physical addresses. Some problems with using physical addresses:

Transferring data that is larger than a page could be a problem because pages in physical memory may not be sequentially mapped.
Suppose there is an ongoing DMA between memory and a frame buffer. If the OS removes some of the pages from physical memory the DMA system has no way to react.

Virtual DMA Solves the previous problems by making the DMA virtually addressable. Special address mapping registers do virtual to physical translations. Non-sequential pages are no longer a problem.